Name
Abstract | ||
|---|---|---|
ABSTRACT Presented high-level synthesis describes scheduling for wide class of DSP algorithms. Several FPGA vendors or even ASIC designs are targeted via Handel-C compiled by Celoxica DK3.1 compiler. Using our approach, the designer can easily change type of used pipelined arithmetic modules and then check new performance. The optimal time schedule is found by cyclic scheduling using Integer Linear Programming,while minimizing,the schedule period in the terms of clock cycles. Experimental results in HW implementation, performed on logarithmic arithmetic and floating-point arithmetic, confirm significant influence of the period on the resulting performance,of DSP algorithms. |
Year | Venue | Keywords |
|---|---|---|
2005 | FPL | high level synthesis,iterative algorithm,floating point arithmetic,linear programming,integer programming,signal processing,field programmable gate arrays,logic design |
Field | DocType | Citations |
Logic synthesis,Handel-C,Computer science,High-level synthesis,Parallel computing,Field-programmable gate array,Compiler,Integer programming,Linear programming,Performance tuning | Conference | 1 |
PageRank | References | Authors |
0.36 | 7 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zdenek Pohl | 1 | 56 | 8.11 |
| sůcha přemysl | 2 | 74 | 13.96 |
| Jiri Kadlec | 3 | 226 | 30.81 |
| hanzalek zdeněk | 4 | 101 | 22.42 |