Name
Title | ||
|---|---|---|
Esd Protection Circuit With Low Triggering Voltage And Fast Turn-On Using Substrate-Triggered Technique |
Abstract | ||
|---|---|---|
In this paper, ESD protection circuit with substrate-triggered technique using PNP bipolar transistor for quick discharge of the electrostatic energy is proposed. The proposed ESD protection circuit is verified by the transmission line pulse (TLP) system. The results show that the proposed ESD protection circuit has lower trigger voltage (5.98 V) compared with that of conventional GGNMOS. And the proposed circuit has faster turn-on time (similar to 37 ns) than that of the conventional substrate-triggered ESD protection circuit. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/elex.6.467 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
ESD, gate grounded NMOS (GGNMOS), Turn on speed | Computer science,Transmission-line pulse,Voltage,Electric potential energy,Electronic engineering,Bipolar junction transistor,Electrical engineering,ggNMOS | Journal |
Volume | Issue | ISSN |
6 | 8 | 1349-2543 |
Citations | PageRank | References |
1 | 0.63 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yong-Seo Koo | 1 | 6 | 6.14 |
| Kwi-Dong Kim | 2 | 70 | 10.44 |
| Jong-Kee Kwon | 3 | 158 | 23.10 |