Name
Abstract | ||
|---|---|---|
An on-chip process, supply voltage, and temperature (PVT) compensation technique for a low-voltage CMOS digital circuit is proposed. Because the degradation of circuit performance originates from the variation of the saturation current, a compensation technique that uses a reference current that is independent of PVT variations was developed. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-mu m standard CMOS parameters. Moreover, Monte Carlo simulations assuming process spread and device mismatch in all MOSFETs showed the effectiveness of the proposed technique and achieved performance improvement of 74%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ISCAS.2009.5118068 | ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 |
Keywords | DocType | Citations |
temperature,monte carlo simulations,low voltage,monte carlo methods,cmos technology,threshold voltage,voltage,monte carlo simulation,chip,low power electronics,transistors,digital circuits,degradation | Conference | 3 |
PageRank | References | Authors |
0.72 | 1 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yusuke Tsugita | 1 | 6 | 1.19 |
| Ken Ueno | 2 | 124 | 13.27 |
| Tetsuya Asai | 3 | 121 | 26.53 |
| Yoshihito Amemiya | 4 | 126 | 33.34 |
| Tetsuya Hirose | 5 | 183 | 38.44 |