Name
Abstract | ||
|---|---|---|
The design of appropriate communication architectures for complex Systems-on-Chip (SoC) is a challenging task. One promising alternative to solve these problems are Networks-on-Chip (NoCs). Recently, the application of deterministic and stochastic Petri-Nets (DSPNs) to model on-chip communication has been proven to be an attractive method to evaluate and explore different communication aspects. In this contribution the modeling of basic NoC communication scenarios featuring different processor cores, network topologies and communication schemes is presented. In order to provide a test bed for the verification of modeling results a state-of-the-art FPGA-platform has been utilized. This platform allows to instantiate a soft-core processor network which can be adapted in terms of communication network topologies and communication schemes. It will be shown that DSPN modeling yields good prediction results at low modeling effort. Different DSPN modeling aspects in terms of accuracy and computational effort are discussed. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/11512622_40 | SAMOS |
Keywords | Field | DocType |
dspn modeling yield,appropriate communication architecture,network topology,different dspn modeling aspect,communication network topology,basic noc communication scenario,communication scheme,stochastic petri net,low modeling effort,different communication aspect,on-chip communication,noc architecture,chip,complex system,core network,network on chip,test bed | Telecommunications network,System on a chip,Petri net,Computer science,Stochastic Petri net,Network topology,Multi-core processor,Deterministic system (philosophy),Distributed computing | Conference |
Volume | ISSN | ISBN |
3553 | 0302-9743 | 3-540-26969-X |
Citations | PageRank | References |
2 | 0.39 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| H. Blume | 1 | 89 | 7.99 |
| T. von Sydow | 2 | 35 | 3.22 |
| D. Becker | 3 | 45 | 5.68 |
| T. G. Noll | 4 | 129 | 13.50 |