Name
Abstract | ||
|---|---|---|
This paper describes a 10b 204MS/s analog-to-digital converter (ADC) employing a pipelined successive approximation register (SAR) architecture for low power consumption and small area. To improve the operation frequency, the pipelined SAR ADC consists of two channels with a proposed asynchronous timing technique. This technique increases the amplification time of a residue opamp. To reduce power and area, the opamp is shared between two channels. A reference buffer with a deglitch circuit reduces the glitch and settling time of reference voltages. The prototype ADC fabricated in a 65nm CMOS process shows a SNDR of 55.2dB and a SFDR of 63.5dB with a 2.4MHz input at 204MS/s. The ADC occupies 0.22mm2 and dissipates 9.15mW at a 1.0V supply. The FoM of the ADC is 95.4fJ/conversion-step. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/CICC.2010.5617457 | CICC |
Keywords | DocType | ISSN |
energy 95.4 fJ,frequency 2.4 MHz,nanofabrication,low power consumption,integrated circuit manufacture,analogue-digital conversion,size 65 nm,asynchronous timing technique,shift registers,power 9.15 mW,SAR ADC,analog-to-digital converter,CMOS digital integrated circuits,CMOS,voltage 1.0 V,successive approximation register architecture | Conference | 0886-5930 |
ISBN | Citations | PageRank |
978-1-4244-5758-8 | 0 | 0.34 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Young-Deuk Jeon | 1 | 98 | 13.50 |
| Young-Kyun Cho | 2 | 19 | 5.05 |
| Jae-Won Nam | 3 | 29 | 6.41 |
| Kwi-Dong Kim | 4 | 70 | 10.44 |
| Woo-Yol Lee | 5 | 25 | 3.05 |
| Kuk-Tae Hong | 6 | 0 | 0.34 |
| Jong-Kee Kwon | 7 | 158 | 23.10 |