Name
Abstract | ||
|---|---|---|
This paper presents a design of 8B/10B encoder with a modified coding table. The proposed encoder has been designed based on a reduced coding table with a modified disparity control block. After being synthesized using CMOS 0.18 mum process, the proposed encoder shows the operating frequency of 343 MHz and occupies the chip area of 1886 mum2 with 189 logic gates. It consumes 2.74 mW power. Compared to conventional approaches, the operating frequency is improved by 25.6% and chip area is decreased to 43%. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/APCCAS.2008.4746322 | APCCAS |
Keywords | Field | DocType |
modified coding table,cmos integrated circuits,8b/10b encoder,encoding,frequency 343 mhz,size 0.18 mum,modified disparity control block,power 3.74 mw,logic gates,cmos,decoding,chip,logic gate,adders | Inverter,Logic gate,Adder,Pass transistor logic,AND-OR-Invert,Computer science,Electronic engineering,Chip,CMOS,Encoder,Computer hardware | Conference |
ISBN | Citations | PageRank |
978-1-4244-2342-2 | 1 | 0.54 |
References | Authors | |
1 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yong-Woo Kim | 1 | 33 | 3.79 |
| Jin-Ku Kang | 2 | 26 | 13.06 |