Name
Abstract | ||
|---|---|---|
Network-on-Chip (NoC) is now considered to be a promising approach to implementing many-core systems and some real-time applications are executed on them. However, it has not yet been proven that on-chip networks can theoretically satisfy the hard real-time constraints. In this paper, we propose the worst-case performance models of on-chip networks which represent the upper bound latency between NoC nodes. We explain when the latency becomes the maximum value and show some evaluation results of the proposed model based on two deadlock-free routing algorithms. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/PRDC.2012.18 | PRDC |
Keywords | Field | DocType |
multiprocessing systems,network routing,network-on-chip,performance evaluation,NoC,deadlock-free routing algorithms,many-core systems,on-chip network,performance analysis,real-time applications,real-time constraints,upper bound latency,worst-case performance modeling,hard real-time constraint,on-chip network,worst-case performance model | Resource management,System on a chip,Computer science,Upper and lower bounds,Network routing,Latency (engineering),Network on a chip,Real-time computing,Distributed computing,Routing algorithm | Conference |
Citations | PageRank | References |
1 | 0.35 | 7 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Masashi Imai | 1 | 47 | 6.24 |
| Tomohiro Yoneda | 2 | 353 | 41.62 |