Name
Title | ||
|---|---|---|
Comparison Frequency Doubling And Charge Pump Matching Techniques For Dual-Band Delta Sigma Fractional-N Frequency Synthesizer |
Abstract | ||
|---|---|---|
The frequency synthesizer with two LC-VCOs is fully integrated in a 0.35-mu m CMOS technology. In supporting dual bands, all building blocks except VCOs are shared. A current compensation scheme using a replica charge pump improves the linearity of the frequency synthesizer and, thus, suppresses spurious tones. To reduce the quantization noise from a Sigma Delta modulator and the noise from the building blocks except the VCO, the proposed architecture uses a frequency doubler with a noise-insensitive duty-cycle correction circuit (DCC) in the reference clock path. Power consumption is 37.8 mW with a 2.7-V supply. The proposed frequency synthesizer supports 10-kHz channel spacing with the measured phase noise of -114 dBc/Hz and -141 dBc/Hz at 100-kHz and 1.25-MHz offsets, respectively, in the PCS band. The fractional spurious tone at 10-kHz offset is under -54 dBc. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/JSSC.2005.857368 | IEEE JOURNAL OF SOLID-STATE CIRCUITS |
Keywords | DocType | Volume |
current mismatch compensation, CMOS RF, frequency doubler, folded noise, fractional-N frequency synthesizers, phase-locked loops, phase noise | Journal | 40 |
Issue | ISSN | Citations |
11 | 0018-9200 | 10 |
PageRank | References | Authors |
1.05 | 11 | 11 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hyungki Huh | 1 | 31 | 5.67 |
| Yido Koo | 2 | 56 | 10.09 |
| Kang-yoon Lee | 3 | 152 | 54.43 |
| Yeonkyeong Ok | 4 | 11 | 1.45 |
| Sungho Lee | 5 | 10 | 1.05 |
| Daehyun Kwon | 6 | 10 | 1.05 |
| Jeong-Woo Lee | 7 | 99 | 27.84 |
| Joonbae Park | 8 | 98 | 17.40 |
| Kyeongho Lee | 9 | 142 | 30.65 |
| Deog-Kyoon Jeong | 10 | 626 | 119.05 |
| W. Kim | 11 | 13 | 1.76 |