Paper Info
Title
An Integrated Memory Array Processor for Embedded Image Recognition Systems
Abstract
Embedded processors for video image recognition in most cases not only need to address the conventional cost (die size and power) versus real-time performance issue, but must also maintain high flexibility due to the immense diversity of recognition targets, situations, and applications. This paper describes IMAP, a highly parallel SIMD linear processor and memory array architecture that addresses these trade-off requirements. By using parallel and systolic algorithmic techniques, but based on a simple linear array architecture, IMAP successfully exploits not only the straightforward per-image row data level parallelism (DLP), but also the inherent DLP of other memory access patterns frequently found in various image recognition tasks, while allowing programming to be done using an explicit parallel C language (1DC). We describe and evaluate IMAP-CE, one of the latest IMAP processors, integrating 128 100 MHz 8 bit 4-way VLIW PEs, 128 2 KByte RAMs, and one 16 bit RISC control processor onto a single chip. The PE instruction set is enhanced to support 1DC code. The die size of IMAP-CE is 11 \times 11 mm^{2} integrating 32.7 M transistors, while the power consumption is, on average, approximately 2 watts. IMAP-CE is evaluated mainly by comparing its performance while running 1DC code with that of a 2.4 GHz Intel P4 running optimized C code. Based on the use of parallelizing techniques, benchmark results show a speed increase of up to 20 times for image filter kernels and of 4 times for a full image recognition application.
Year
DOI
Venue
2007
10.1109/TC.2007.1010
IEEE Trans. Computers
Keywords
Field
DocType
bit risc control processor,explicit parallel c language,latest imap processor,array processor,various image recognition task,recognition target,image filter kernel,image recognition systems,simd linear processor,optimized c code,full image recognition application,integrated memory,video image recognition,data level parallelism,image processing,transistors,reduced instruction set computing,real time,vliw,parallel algorithms,parallel programming,embedded processor,process control,embedded systems,chip,instruction sets,image recognition,linear programming
Computer vision,Parallel language,Computer science,Instruction set,Very long instruction word,16-bit,Parallel computing,SIMD,Chip,Data parallelism,Reduced instruction set computing,Artificial intelligence
Journal
Volume
Issue
ISSN
56
5
0018-9340
Citations 
PageRank 
References 
14
1.47
22
Authors
3
Name
Order
Citations
PageRank
Shorin Kyo18510.66
Shin'ichiro Okazaki210314.26
Tamio Arai31087189.91