Name
Abstract | ||
|---|---|---|
The high performance switch plays a critical role in the high performance computer (HPC) system. The applications of HPC not only demand on the low latency and high bandwidth of the switch, but also need the effective support of collective communication, such as broadcast, multicast, and barrier etc. In this paper, HPP switch, as the core component of interconnection network of a HPC prototype, is introduced to meet these requirements. It is with 38.4 ns zero-load latency, 160 Gbps aggregated bandwidth, 16 multicast groups and 16 barrier groups. HPP switch is implemented in a 0.13 mum CMOS standard cell ASIC technology. The simulation results show that the multicast and barrier operations for 1024 nodes are finished within 2 mus, and the single stage of barrier operation only needs 128 ns. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/HOTI.2008.17 | Hot Interconnects |
Keywords | DocType | ISSN |
cmos standard cell,cmos integrated circuits,multicast group,high bandwidth,high performance switch,aggregated bandwidth,zero-load latency,novel high performance switch,hpp switch,barrier etc.,interconnection network,application specific integrated circuits,microswitches,barrier group,high performance computer,asic technology,size 0.13 mum,hpc prototype,barrier operation,bandwidth,hardware,switches,synchronization,throughput,prototypes,unicast | Conference | 1550-4794 |
ISBN | Citations | PageRank |
978-0-7695-3380-3 | 3 | 0.42 |
References | Authors | |
11 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dawei Wang | 1 | 3 | 1.09 |
| Zheng Cao | 2 | 5 | 1.58 |
| Xinchun Liu | 3 | 67 | 5.65 |
| SUN Ning-Hui | 4 | 1268 | 97.37 |