Title
Low cost scaleable parallel image processing system
Abstract
The design and application of a DSP-based Parallel Image Processing system is presented. A scaleable system based around a TMS320C40 DSP Master–Slave architecture is shown to be a suitable vehicle for industrial inspection problems. Custom vision bus and parallel communication channels are used to pass data between local and shared memory in the image processing system. The target application of SMT solder bond inspection required the fast processing of 2-D FFTs. Analysis of the system's suitability to this task is presented followed by actual results from a three-processor system. The target inspection rate of 100 SMT solder joints per second can be met.
Year
DOI
Venue
2001
10.1016/S0141-9331(01)00107-7
Microprocessors and Microsystems
Keywords
Field
DocType
Image processing,Parallel architectures,PCB inspection,Industrial inspection,2D FFT,TMS320C40 DSP
Digital signal processing,Shared memory,Parallel communication,Computer science,Parallel computing,Image processing,Communication channel,Parallel image processing,Computer hardware,Industrial inspection,Embedded system
Journal
Volume
Issue
ISSN
25
3
0141-9331
Citations 
PageRank 
References 
1
0.40
8
Authors
3
Name
Order
Citations
PageRank
David M. Harvey162.50
Shirish P. Kshirsagar210.40
C.Allan Hobson310.40