Name
Abstract | ||
|---|---|---|
A mobile sensor system for very low level biological signals such as neuron spikes is required to implement with a scaled CMOS technology. For a key circuit of these systems, a chopper amplifier (CA) which suppresses DC offset and 1/f noise of MOS devices is widely used. However, the conventional CA consumes large power because it requires a wide-band amplifier exceed a chopping frequency and a post Low Pass Filter (LPF) for eliminating modulation noise. In this paper, a new CA architecture for reducing power consumption is presented. In the architecture, the demodulator is placed at the input of 2nd stage amplifier and the 2nd stage has a narrow band determined with a 1st pole. Moreover the post LPF is not required. The proposed CA was designed and simulated with a 0.18 mu m CMOS process and a 1.2 V supply. When the ratio of chopping frequency and signal band width is set to 100 (= 10 kHz/100 Hz), the power consumption of the CA is reduced to 1/88 (= 7 mu W/616 mu W) compared with the conventional CA. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1587/elex.5.967 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
flicker noise, chopper AMP, low-power, low-noise | Flicker noise,Computer science,Electronic engineering,CMOS,Modulation,Low-pass filter,DC bias,Low voltage,Chopper,Electrical engineering,Amplifier | Journal |
Volume | Issue | ISSN |
5 | 22 | 1349-2543 |
Citations | PageRank | References |
2 | 0.48 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshihiro Masui | 1 | 7 | 2.66 |
| Takeshi Yoshida | 2 | 30 | 9.22 |
| Atsushi Iwata | 3 | 30 | 8.84 |