Name
Abstract | ||
|---|---|---|
A novel approach for gate-matrix synthesis starting from an EDIF logical network description is presented. The networks are automatically decomposed into gate-matrix 'macrocells' with approximately equal layout area using a very effective algorithm, which is adapted to the layout topology, featuring simultaneous module placement in conjunction with a new reliable module area estimation technique.Dramatic improvements in overall layout generation time and layout area are achieved; area savings are significantly higher than previously reported. |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1109/EDAC.1990.136668 | EURO-DAC |
Keywords | Field | DocType |
recursive partitioning,generation time,optimization,quadratic assignment problem | Integrated circuit layout,Matrix (mathematics),Quadratic assignment problem,Computer science,IC layout editor,Theoretical computer science,Recursive partitioning,Standard cell,Register-transfer level,Design layout record,Computer engineering | Conference |
ISBN | Citations | PageRank |
0-8186-2024-2 | 0 | 0.34 |
References | Authors | |
5 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Frank H. Huentemann | 1 | 0 | 0.34 |
| Utz G. Baitinger | 2 | 0 | 3.04 |