Paper Info
Title
A Thread Speed Control Scheme for Real-Time Microprocessors
Abstract
Real-time execution of applications is one of key requirements for Cyber-Physical Systems (CPS) that integrate computational and physical elements for our social infrastructure, such as robotics, transportation, and consumer appliances. In such real-time systems, a task must be executed so as not to violate given time constraints. Moreover, it is desirable that the execution time of the task is predictable precisely. When Out-of-Order (OoO) execution is adopted for real-time systems to enhance the performance, it is much difficult to predict execution time because of the feature of OoO execution. In order to deal with this problem, various schemes were proposed such as IPC control mechanism of Responsive Multithreaded (RMT) Processor. RMT Processor is a real-time microprocessor adopting simultaneous multithreading (SMT) architecture with OoO execution. Its IPC control mechanism which tries to adjust the number of instruction commits to meet a given target IPC. The IPC control scheme can be implemented not only on RMT Processor but also on various processors and can improve the predictability of execution time. However, if an error between target and actual IPCs is observed, it cannot cancel the error in the next control window, which is used in the control mechanism. Since such uncorrected errors are accumulated in the successive control window, the predictability of the execution time is degraded gradually. To overcome this problem, in this paper, we propose a thread speed control scheme for real-time microprocessors. This scheme is based on the IPC control mechanism on RMT Processor. Our proposed thread speed control scheme calculates an error between reference and actual IPCs, then it dynamically updates the reference IPC of the next control window in order to cancel the past errors. Our proposed scheme is designed and implemented on RMT Processor. The simulation results show that the error is reduced to 2.60 聛~ 10^5 % in case that four threads are executed simultaneously.
Year
DOI
Venue
2011
10.1109/RTCSA.2011.77
RTCSA (2)
Keywords
Field
DocType
successive control window,execution time,ipc control scheme,proposed thread speed control,thread speed,next control window,ipc control mechanism,real-time microprocessors,control mechanism,control scheme,ooo execution,rmt processor,real-time system,registers,computer architecture,real time,instruction sets,multi threading,out of order,real time system,process control,real time systems,speed control,simultaneous multithreading,cyber physical systems
Multithreading,Instruction set,Computer science,Microprocessor,Real-time computing,Thread (computing),Real-time operating system,Simultaneous multithreading,Process control,Electronic speed control,Embedded system
Conference
ISSN
Citations 
PageRank 
1533-2306
0
0.34
References 
Authors
4
3
Name
Order
Citations
PageRank
Kohei Matsumoto101.69
Hiroyuki Umeo200.34
Nobuyuki Yamasaki333830.45