Name
Title | ||
|---|---|---|
FPGA-based acceleration of cascaded support vector machines for embedded applications (abstract only) |
Abstract | ||
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Support Vector Machines (SVMs) are considered one of the most popular classification algorithms yielding high accuracy rates. However, SVMs often require processing a large number of support vectors, making the classification process computationally demanding, and hence it is challenging to meet real-time processing constraints imposed by many embedded applications. In order to improve SVM classification times the cascade classification scheme has been proposed. However, even in this case real-time performance is still challenging to achieve without exploiting the throughput and processing requirements of each cascade stage. Hence the design of an FPGA-based accelerator for cascaded SVM processing is proposed; in addition to a hardware reduction method in order to reduce the implementation requirements of the cascade SVM leading to significant resource savings. The accelerator was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640×480 resolution images. It was compared against FPGA implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. The accelerator is capable an average performance of 70 frames-per-second, achieving a speed-up of 5× over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less FPGA LUT resources, with only 0.7% reduction in classification accuracy. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1145/2435264.2435316 | FPGA |
Keywords | DocType | Citations |
cascaded support vector machine,fpga-based acceleration,cascade classification scheme,cascaded svm processing,classification accuracy,cascade processing architecture,popular classification,cascade svm,svm classification time,classification process computationally,processing requirement,embedded application,single parallel svm classifier,fpga,support vector machines | Conference | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christos Kyrkou | 1 | 102 | 14.05 |
| Christos Savvas Bouganis | 2 | 400 | 49.04 |
| Theocharis Theocharides | 3 | 205 | 26.83 |