Name
Abstract | ||
|---|---|---|
Memories are among the densest integrated circuits that can be fabricated and therefore, have the highest rate of defects. This paper discusses an efficient technique for designing low cost high defect tolerant RAM chips. A 25% improvement in the yield is presented. The paper proposes a scheme that selects the right redundancy in memory designs driven by the fabrication cost and the yield. The new memory chip design technique fills the gap between the existing all-or-none extremes with memories. The area is sacrificed for these performance improvements, for significant power savings as well as for the significant improvement in the yield. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1366224.1366229 | Proceedings of the 2008 workshop on Radiation effects and fault tolerance in nanometer technologies |
Keywords | DocType | Citations |
memory design,low power,new memory chip design,power aware low cost,high defect tolerant,efficient technique,fabrication cost,densest integrated circuit,high defect tolerant ram,low cost,significant improvement,performance improvement,performance,significant power saving,yield improvement,existing all-or-none extreme,integrated circuit,chip | Conference | 0 |
PageRank | References | Authors |
0.34 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Costas Argyrides | 1 | 91 | 11.20 |
| Stephania Loizidou Himona | 2 | 17 | 1.38 |
| Dhiraj K. Pradhan | 3 | 2670 | 452.20 |