Paper Info
Title
Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation.
Abstract
In this paper, aiming toward a compact high-throughput reconfigurable architecture, we propose the reconfigurable processor DS-HIE. hi order to achieve the characteristics of compactness and high-throughput, the DS-HIE architecture executes operations following a bit-serial computation scheme and adopts a Benes network as its routing resource. Implementing bit-serial computation brings the advantage of small chip area and high throughput to the DS-HIE architecture, and the Benes network ensures the high availability of the routing paths within a compact chip area. In this paper, we evaluated its transistor count and performance, compared with the RISC processor MeP. From this evaluation, the DS-HIE processor required 9.2 times the transistor count of the MeP processor, it achieved 13 to 33 times higher performance as compared with the MeP processor.
Year
DOI
Venue
2008
10.1109/FPT.2008.4762396
FPT
Keywords
Field
DocType
microprocessor chips,performance evaluation,reconfigurable architectures,reduced instruction set computing,Benes network,DS-HIE reconfigurable processor,MeP RISC processor,bit-serial computation,compact high-throughput reconfigurable architecture,performance evaluation,routing resource,transistor count
Transistor count,Architecture,Computer science,Parallel computing,Chip,Reduced instruction set computing,Throughput,Transistor,High availability,Embedded system,Computation
Conference
Citations 
PageRank 
References 
1
0.41
2
Authors
2
Name
Order
Citations
PageRank
Kazuya Tanigawa163.33
Tetsuo Hironaka2149.36