Name
Abstract | ||
|---|---|---|
A high-scale integrated optical receiver including a preamplifier, a limiting amplifier, a clock and data recovery (CDR) block,
and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25 μm CMOS technology. Using the loop parameter optimization method
and the low-jitter circuit design technique, the rms and peak-to-peak jitter of the recovered 625 MHz clock are 9.4 and 46.3
ps, respectively, which meet the jitter specifications stipulated in ITU-T recommendation G.958. In response to 2.5 Gb/s PRBS
input data (223−1), the recovered and frequency divided 625 MHz clock has a phase noise of −83.8 dBc/Hz at 20 kHz offset and the 2.5 Gb/s
PRBS data has been demultiplexed into four 625 Mb/s data. The power dissipation is only 0.3 W under a single 3.3 V supply
(excluding output buffers). |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1007/s11432-011-4218-7 | SCIENCE CHINA Information Sciences |
Keywords | Field | DocType |
phase noise,circuit design,power dissipation | Demultiplexer,Preamplifier,Control theory,Circuit design,Phase noise,Real-time computing,CMOS,Multiplexer,dBc,Jitter,Electrical engineering,Mathematics | Journal |
Volume | Issue | ISSN |
54 | 6 | 1869-1919 |
Citations | PageRank | References |
1 | 0.42 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| YingMei Chen | 1 | 24 | 3.53 |
| Zhigong Wang | 2 | 29 | 21.30 |
| Li Zhang | 3 | 1 | 0.42 |