Name
Abstract | ||
|---|---|---|
Clock distribution networks consume a considerable portion of the power dissipated by synchronous circuits. In conventional clock distribution networks, clock buffers are inserted to retain signal integrity along the long interconnects, which, in turn, significantly increase the power consumed by the clock distribution network. Resonant clock distribution networks are considered as efficient lowpower alternatives to traditional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. A design method for applying the resonant clocking approach for synthesized clock trees is presented. The proper number and placement of LC tanks and the related resonance parameters are determined in the proposed method. This method attempts to minimize the number of LC tanks that can deliver a full swing signal to all the sink nodes by considering the capacitive load at each node to determine the location of LC tanks. Resonance parameters, such as the size of the inductor can be adapted to reduce the power consumption and/or area overhead of the clock distribution network. Simulation results indicate up to 57% reduction in the power consumed by the resonant clock network as compared to a conventional buffered clock network. Compared to existing methods, the number of LC tanks for the proposed technique is decreased up to 15% and the signal swing is also improved by 44%. Depending on whether power or area is the design objective, two different approaches are followed to determine the parameters of resonance. If the design objective is to lower the power consumed by the network, the power and area of the designed network improve up to 24% and 51%, respectively, as compared to state of the art methods. If a low area is targeted, the power and area improvements are 11% and 57%, respectively. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1166/jolpe.2013.1250 | JOURNAL OF LOW POWER ELECTRONICS |
Keywords | Field | DocType |
3-D Integration, Resonant Clocking, LC Tank | Clock signal,Clock gating,Overclocking,Clock network,Underclocking,Electronic engineering,Real-time computing,Synchronous circuit,Clock skew,Engineering,CPU multiplier,Electrical engineering | Journal |
Volume | Issue | ISSN |
9 | 2 | 1546-1998 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Somayyeh Rahimian | 1 | 4 | 1.12 |
| Vasilis F. Pavlidis | 2 | 148 | 19.15 |
| Xifan Tang | 3 | 59 | 12.89 |
| Giovanni De Micheli | 4 | 10245 | 1018.13 |