Name
Abstract | ||
|---|---|---|
This paper discusses propagation delay error, transient response, and power consumption distribution due to inductive effects in optimal buffered on-chip interconnects. Inductive effect is said to be important to consider in deep submicron (DSM) VLSI design. However, study shows that the effect decreases and can be neglected in next technology nodes for such conditions. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1093/ietele/e89-c.3.392 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
on-chip interconnects, deep sub-micron, inductive effect, signal integrity | Transient response,Propagation delay,Signal integrity,Electronic engineering,Integrated circuit design,Engineering,Miniaturization,Interconnection,Electrical engineering,Very-large-scale integration,Integrated circuit | Journal |
Volume | Issue | ISSN |
E89C | 3 | 1745-1353 |
Citations | PageRank | References |
2 | 0.41 | 1 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Danardono Dwi Antono | 1 | 4 | 1.14 |
| Kenichi Inagaki | 2 | 26 | 3.50 |
| Hiroshi Kawaguchi | 3 | 395 | 91.51 |
| Takayasu Sakurai | 4 | 38 | 4.53 |