Name
Abstract | ||
|---|---|---|
Evaluating the performance measures of a full adder cell, like other circuits, is input pattern dependent. The issue gets more complicated when evaluating several parameters such as time delay, area, power dissipation, and correct functionality at the same time. The proposed input test pattern is based on full coverage of all possible transitions from one input pattern to another. It is composed of two parts, first is a 56 transitions input pattern for speed measurement, followed by 9 different input patterns concatenated together for power consumption measurement. The proposed input test pattern proves the correct functionality, and produces correct time delay and power dissipation. Using this input test pattern guarantees correct and fair comparison among different full adder cells. |
Year | DOI | Venue |
|---|---|---|
1999 | 10.1109/ISCAS.1999.777797 | ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI |
Keywords | Field | DocType |
time measurement,adders,automatic test pattern generation,area,power dissipation,voltage | Automatic test pattern generation,Speed measurement,Adder,Dissipation,Computer science,CMOS,Electronic engineering,Concatenation,Electronic circuit,Power consumption | Conference |
Citations | PageRank | References |
8 | 1.90 | 3 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ahmed M. Shams | 1 | 96 | 10.75 |
| Magdy A. Bayoumi | 2 | 803 | 122.04 |