Paper Info
Title
Performance Improvement for H.264 Video Encoding using ILP Embedded Processor
Abstract
In this paper, we examine the impact of instruction level parallelism (ILP) on the full H.264 video encoding application and give quantitative performance measures of a superscalar architecture. Most research efforts have concentrated on the data intensive parts, such as kernels but these are taking less time from the entire execution as encoders are using new, more efficient algorithms. This important fact cannot be neglected since new video encoding standards have been proposed and the amount of other than data intensive computations has increased significantly. We observed significant improvement for the entire application when using superscalar architecture with out-of-order execution scheme. Tradeoffs in superscalar performance are also evaluated with combinations of measurements from SimpleScalar simulator.
Year
DOI
Venue
2006
10.1109/DSD.2006.77
DSD
Keywords
Field
DocType
code standards,embedded systems,parallel processing,video coding,H.264 video encoding standards,data intensive computations,instruction level parallelism embedded processor,out-of-order execution scheme,performance improvement,simplescalar simulator,superscalar architecture
Instruction-level parallelism,Video encoding,Computer science,Parallel computing,Parallel processing,Real-time computing,Encoder,Superscalar,Embedded system,Performance improvement,Computation
Conference
ISBN
Citations 
PageRank 
0-7695-2609-8
1
0.36
References 
Authors
8
2
Name
Order
Citations
PageRank
Ali R. Iranpour1131.69
K. Kuchcinski2928.47