Name
Abstract | ||
|---|---|---|
In this paper, we present the formal transformation of Timed Input/Output Automata into simulation models, expressed in the DEVS formalism. This transformation takes place in an approach of a validation of high-level specifications by simulation. The validation is based on the simulation of a coupled model built with the system to be controlled and the control specifications. An example of this approach is given in the paper. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.5555/1030818.1030939 | Winter Simulation Conference |
Keywords | Field | DocType |
control specification,simulation model,verification ii,high-level specification,formal transformation,timed input,devs formalism,devs model,output automata,input output | SP-DEVS,Simulation,Computer science,Automaton,Simulation modeling,Theoretical computer science,Timed automaton,DEVS,Formalism (philosophy) | Conference |
ISBN | Citations | PageRank |
0-7803-8132-7 | 6 | 0.70 |
References | Authors | |
10 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Norbert Giambiasi | 1 | 227 | 37.59 |
| Jean-Luc Paillet | 2 | 9 | 5.39 |
| Frédéric Châne | 3 | 7 | 1.06 |