Name
Abstract | ||
|---|---|---|
This paper presents a design method for fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on quantization error. Then, different error compensation methods are applied to each group. By simulation, it is shown that the performance of the proposed method is pretty close to that of the rounding operation and much better than that of the truncation operation. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/ISCAS.2003.1206210 | ISCAS |
Keywords | Field | DocType |
digital arithmetic,error compensation,integrated circuit design,integrated logic circuits,logic design,quantisation (signal),Booth encoder outputs,Booth folding technique,error compensation bias,error compensation methods,fixed-width squarer,low-error squarer design,quantization error | Compensation methods,Control theory,Computer science,Round-off error,Error detection and correction,Rounding,Multiplier (economics),Electronic engineering,Vector quantization,Encoder,Quantization (signal processing) | Conference |
Volume | Citations | PageRank |
5 | 2 | 0.50 |
References | Authors | |
0 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| K. J. Cho | 1 | 7 | 1.14 |
| E. M. Choi | 2 | 2 | 0.50 |
| J. G. Chung | 3 | 7 | 1.14 |
| M. S. Lim | 4 | 2 | 0.50 |
| J. W. Kim | 5 | 2 | 0.50 |