Name
Title | ||
|---|---|---|
Formal verification of superscale microprocessors with multicycle functional units, exception, and branch prediction |
Abstract | ||
|---|---|---|
We extend the Burch and Dill flushing technique [6] for formal verification of microprocessors to be applicable to designs where the functional units and memories have multicycle and possibly arbitrary latency. We also show ways to incorporate exceptions and branch prediction by exploiting the properties of the logic of Positive Equality with Uninterpreted Functions [4][5]. We study the modeling of the above features in different versions of dual-issue superscalar processors. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1145/337292.337331 | DAC |
Field | DocType | ISSN |
Permission,Computer aided instruction,Computer science,Parallel computing,Electronic engineering,Electronic design automation,Superscalar,Branch predictor,Hierarchical test,Formal verification | Conference | 0738-100X |
ISBN | Citations | PageRank |
1-58113-187-9 | 62 | 3.29 |
References | Authors | |
22 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Miroslav N. Velev | 1 | 953 | 60.17 |
| Randal E. Bryant | 2 | 9204 | 1194.64 |