Name
Abstract | ||
|---|---|---|
In this paper a partly unified hardware/software design flow is presented. It uses SystemC as system level design language and postpones the partitioning decision to a lower abstraction level by using a realization independent functional model. Especially the partitioning of data flow dominant tasks between hardware and software is simplified with this approach. Additionally, by using a C-based design language for hardware and software design, system simulations at different abstraction levels are simplified. In combination with the concept of high level synthesis, this design flow reduces the effort after the partitioning and thus also significantly reduces the extra effort of a possible repartitioning between hardware and software. As proof of concept the receiver components of a VoIP engine have been implemented. The data flow dominant RTP protocol has been realized on an FPGA and the results of different hardware/software partitionings are presented. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/AMS.2009.18 | Asia International Conference on Modelling and Simulation |
Keywords | Field | DocType |
data flow analysis,field programmable gate arrays,hardware description languages,hardware-software codesign,FPGA,RTP protocol,SystemC functional models,VoIP engine,data flow dominant tasks,hardware/software design flow,hardware/software partitioning,FPGA,Hardware/Software Codesign,High Level Synthesis,Partitioning,Signal Processing,SystemC,VoIP | Computer architecture,Software design,Computer science,High-level synthesis,Electronic system-level design and verification,SystemC,Software,Software construction,Hardware description language,Hardware architecture | Conference |
Citations | PageRank | References |
1 | 0.35 | 5 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Peter Brunmayr | 1 | 2 | 1.50 |
| Jan Haase | 2 | 65 | 8.01 |
| Florian Schupfer | 3 | 23 | 3.64 |