A Two-pole Circuit Model for VLSI High-speed Interconnection - Citegraph

Paper Info

Title
A Two-pole Circuit Model for VLSI High-speed Interconnection

Year	DOI	Venue
1993	10.1109/ISCAS.1993.394178	ISCAS
Field	DocType	Citations
Integrated circuit layout,Capacitance,Computer science,Tree (data structure),Electronic engineering,Electrical impedance,Network topology,Interconnection,RLC circuit,Very-large-scale integration	Conference	2
PageRank	References	Authors
0.45	1	5

Authors (5 rows)

Cited by (2 rows)

References (1 rows)

Name	Order	Citations	PageRank
Dian Zhou	1	17	3.39
S. Su	2	2	0.45
F. Tsui	3	2	0.78
D. S. Gao	4	21	5.35
Jason Cong	5	7069	515.06

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