Title
Design of highly linear multipliers using floating gate transistors and/or source degeneration resistor
Abstract
Compact schemes to implement two highly linear four quadrant CMOS transconductance multipliers are presented in this work. They are based on floating gate transistors and/or source degeneration resistor which provide high linearity and wide input, output swing. Two cross connected differential pairs are used as current steering elements which provide continuous adjustable gain. Unlike the conventional multipliers the proposed techniques generate currents that have mostly linear terms and reduce cancellation of non-linear terms at the output. Hence they are very linear and non-vulnerable to practical problems like mismatch and finite output impedance. Simulation and Experimental results are provided which validate the proposed schemes.
Year
DOI
Venue
2008
10.1109/ISCAS.2008.4541712
ISCAS
Keywords
Field
DocType
analogue multipliers,integrated circuit design,resistors,transistors,cross connected differential pairs,current steering elements,floating gate transistors,linear four quadrant CMOS transconductance multipliers,source degeneration resistor
Output impedance,Computer science,Control theory,Linearity,Electrical impedance,Electronic engineering,CMOS,Resistor,Integrated circuit design,Transconductance,Electronic circuit
Conference
ISSN
Citations 
PageRank 
0271-4302
2
0.74
References 
Authors
0
4