Paper Info
Title
An Analysis Framework for Transient-Error Tolerance
Abstract
Transient or soft errors are an increasing problem in mainstream microelectronics. We propose a framework for modeling transient-error tolerance (TET) in logic circuits. We classify transient errors as critical or non-critical according to their impact on circuit behavior, such as their ability to disturb the internal state for specified periods of time. We introduce a metric called the critical soft-error rate (CSER) as an alternative to conventional SER, and present some analysis strategies based on CSER. This approach employs a new single transient fault (STF) model, which is defined in terms of a temporary stuck-at fault and its associated circuit state. Although basically technology-independent, STFs can be extended with low-level physical attributes. With STFs, we can estimate the transient error probability perr of a circuit's nodes, as well as various measures of error susceptibility and TET. We demonstrate the use of STFs with combinational and sequential circuits, including several types of adders. We also present a systematic hardening strategy that uses perr as a guide to improving TET.
Year
DOI
Venue
2007
10.1109/VTS.2007.13
VTS
Keywords
Field
DocType
adders,combinational circuits,fault simulation,logic testing,probability,sequential circuits,adders,circuit behavior,combinational circuits,critical soft-error rate,logic circuits,sequential circuits,single transient fault model,soft errors,temporary stuck-at fault,transient error probability,transient-error tolerance
Logic gate,Sequential logic,Adder,Computer science,Error tolerance,Algorithm,Error detection and correction,Combinational logic,Real-time computing,Electronic engineering,Transient analysis,Probability of error
Conference
ISSN
ISBN
Citations 
1093-0167
0-7695-2812-0
32
PageRank 
References 
Authors
1.99
14
3
Name
Order
Citations
PageRank
J. P. Hayes13592501.80
Ilia Polian288978.66
B. Becker319121.44