Name
Abstract | ||
|---|---|---|
A set of graph augmentation algorithms are introduced to model a class of timing faults in timed-EFSM models. It is shown that the test sequences generated based on our models can detect 1-clock and n-clock timing faults, and incorrect timer setting faults in an implementation under test (IUT). It is proven that the size of the augmented graph resulting from our augmentation algorithms is in the same order of magnitude as of the original specification. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TC.2007.70772 | IEEE Trans. Computers |
Keywords | Field | DocType |
graph augmentation algorithm,incorrect timer,timing fault,n-clock timing fault,augmented graph,original specification,augmentation algorithm,single timing faults,communication protocols,timed-efsm model,test sequence,graph theory,finite state machine,extended finite state machine,fault model,communication protocol,automatic test pattern generation,conformance testing,protocols,finite state machines | Graph theory,Automatic test pattern generation,Computer science,Automaton,Algorithm,Extended finite-state machine,Finite-state machine,Real-time computing,Timer,Statistical classification,Communications protocol | Journal |
Volume | Issue | ISSN |
57 | 2 | 0018-9340 |
Citations | PageRank | References |
13 | 0.99 | 21 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Umit Uyar | 1 | 62 | 8.24 |
| Samrat S. Batth | 2 | 36 | 3.35 |
| Yu Wang | 3 | 31 | 6.65 |
| Mariusz A. Fecko | 4 | 126 | 11.98 |