Name
Abstract | ||
|---|---|---|
A multistage self-routing permutation network is presented. This network is constructed from concentrators and digit-controlled $2 \times 4$ switches. A destination-tag routing scheme is used to realize any arbitrary permutation. The network has $O(log^2\ N)$ gate-delay and uses $O(N^2)$ VLSI-area, where N is the number of inputs.1 Assuming packet-switching is used for message transmission, the delay and VLSI-area of the network are smaller than those of any self-routing permutation network presented to date. |
Year | DOI | Venue |
|---|---|---|
1995 | 10.1109/12.372036 | IEEE Trans. Computers |
Keywords | DocType | Volume |
message transmission,arbitrary permutation,Fast VLSI-Efficient Self-Routing Permutation,destination-tag routing scheme,self-routing permutation network,permutation network | Journal | 44 |
Issue | ISSN | Citations |
3 | 0018-9340 | 2 |
PageRank | References | Authors |
0.41 | 2 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jose A. B. Fortes | 1 | 446 | 52.01 |
| Hasan Cam | 2 | 143 | 22.81 |