Name
Title | ||
|---|---|---|
Achieving efficient packet-based memory system by exploiting correlation of memory requests |
Abstract | ||
|---|---|---|
Packet-based interface is a trend for future memory system to alleviate memory capacity and bandwidth bottlenecks. On the other hand fine-grained memory access has been proven to efficiently reduce memory power. However leveraging both these two technologies will result in high packet overhead, because previous implementations of packet-based interface all adopt a simple design that a single packet is dedicated to a single request (SPSR). In this paper, we propose three optimizations to overcome the problem by exploiting correlations of memory requests. First, we propose a novel single packet multiple requests (SPMR) interface that encapsulates multiple requests into a packet to share packet header and tail. Second, we propose an adaptive address compression mechanism within a packet by adopting a base-difference algorithm. Third, we propose a mechanism to merge multiple memory requests with continuous access addresses into a single request before packing. By this way, the granularity constraint of cache line size is broken to enable efficiently row buffer scheduling. The experimental results show that, for certain memory-intensive workloads, the optimizations can effectively reduce packet overhead by about 53.9% and improve system performance by about 63.6% in average. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.7873/DATE.2014.090 | DATE |
Keywords | Field | DocType |
optimisation,adaptive address compression mechanism,single packet single request,novel single packet,dram chips,packet-based interface,packet overhead,fine grained memory access,memory requests,efficient packet-based memory system,high packet overhead,share packet header,single request,single packet multiple requests interface,bandwidth bottlenecks,multiple request,hand fine-grained memory access,granularity constraint,single packet,future memory system,packet based memory system,packet based interface,memory capacity,row buffer scheduling,memory request,system on chip,layout,payloads,bandwidth,optimization,market research | Packet segmentation,Interleaved memory,Uniform memory access,Computer science,Parallel computing,Transmission delay,Real-time computing,Memory management,Packet generator,Fast packet switching,Processing delay | Conference |
ISSN | Citations | PageRank |
1530-1591 | 2 | 0.37 |
References | Authors | |
19 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tianyue Lu | 1 | 8 | 3.26 |
| Licheng Chen | 2 | 103 | 9.74 |
| Ming-yu Chen | 3 | 902 | 79.29 |