Name
Abstract | ||
|---|---|---|
This paper presents an efficient algorithm for post-synthesis logic simulation of digital circuits with oscillatory combinational loops. Oscillatory combinational loops can significantly degrade the performance of cycle accurate logic simulators. We provide an algorithm that first, dynamically detects oscillatory loops. Then, we introduce a novel approach to compute a multiple of their oscillation period which is used to optimize the efficiency of the simulation by reducing the number of time points that need to be evaluated. Finally, we provide the experimental results of our optimized algorithm measured on a cycle accurate simulator used in conjunction with a hardware emulator. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1837274.1837470 | DAC |
Keywords | Field | DocType |
oscillatory loop,dynamically detects,optimized algorithm,digital circuit,post-synthesis logic simulation,cycle accurate logic simulator,oscillatory combinational loop,cycle accurate simulator,efficient algorithm,efficient simulation,stability analysis,computational modeling,integrated circuit design,logic design,hardware,logic gates,functional verification,oscillators,graphics,digital circuits,oscillations,logic circuits,emulation,combinational circuits | Logic synthesis,Digital electronics,Logic gate,Functional verification,Computer science,Electronic engineering,Combinational logic,Emulation,Integrated circuit design,Logic simulation | Conference |
ISSN | Citations | PageRank |
0738-100X | 0 | 0.34 |
References | Authors | |
5 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Morteza Fayyazi | 1 | 9 | 1.64 |
| Laurent Kirsch | 2 | 2 | 1.39 |