Name
Abstract | ||
|---|---|---|
In modern wireline and wireless communication systems, Viterbi decoder is one of the most compute intensive and essential elements. Each standard requires a different configuration of Viterbi decoder. Hence there is a need to design a flexible reconfigurable Viterbi decoder to support different configurations on a single platform. In this paper we present a reconfigurable Viterbi decoder which can be reconfigured for standards such as WCDMA, CDMA2000, IEEE 802.11, DAB, DVB, and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. Our design provides higher throughput and scalable power consumption in various configuration of the reconfigurable Viterbi decoder. The power and throughput can also be optimized for different standards. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/ASAP.2008.4580153 | ASAP |
Keywords | Field | DocType |
different standard,scalable power consumption,reconfigurable viterbi decoder,wcdma,ieee 802.11,different configuration,cdma2000,mesh connected multiprocessor architecture,viterbi decoding,gsm,constraint length,radio networks,dab,multiprocessor architecture,viterbi decoder,higher throughput,different parameter,flexible reconfigurable viterbi decoder,truncation length,dvb,viterbi algorithm,ieee 802 11,generators,polynomials,registers,wireless communication,computer architecture,decoding,digital video broadcasting,throughput | GSM,Code rate,Computer science,Real-time computing,CDMA2000,Viterbi decoder,Soft-decision decoder,Digital Video Broadcasting,Throughput,Viterbi algorithm | Conference |
ISSN | ISBN | Citations |
2160-0511 E-ISBN : 978-1-4244-1898-5 | 978-1-4244-1898-5 | 1 |
PageRank | References | Authors |
0.36 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ritesh Rajore | 1 | 2 | 0.72 |
| Ganesh Garga | 2 | 1 | 1.37 |
| H. S. Jamadagni | 3 | 160 | 30.14 |
| S. K. Nandy | 4 | 320 | 50.83 |