Name
Abstract | ||
|---|---|---|
Technology trends are driving parallel on-chip architectures in the form of multiprocessor systems-on-a-chip (MPSoCs) and chip multiprocessors (CMPs). In these systems, the increasing on-chip communication demand among the computation elements necessitates the use of scalable, high-bandwidth network-on-chip (NoC) fabrics instead of dedicated interconnects and shared buses. As transistor feature sizes are further miniaturized, more complicated NoC architectures become feasible that can support more demanding applications. Given the myriad emerging software-hardware combinations, for cost-effectiveness, a system designer critically needs to prune this widening NoC design-space to predict the interconnect fabric(s) that best balance(s) cost/performance, before the actual design process begins. This prompted us to develop Polaris, a system-level roadmapping toolchain for on-chip interconnection networks that helps designers predict the most suitable interconnection network design(s) tailored to their performance needs and power/silicon area constraints with respect to a range of applications that the system will run. Polaris explores the plethora of NoC designs based on projections of network traffic, architectures, and process characteristics. While Polaris's toolchain is extensible so new traffic, network designs, and technology processes can be added, the current version already incorporates 7872 NoC design points. Polaris is rapid, efficiently iterating over thousands of NoC design points, while maintaining high relative and absolute accuracies when validated against detailed NoC synthesis results. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/TVLSI.2007.900725 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
widening noc design-space,on-chip communication demand,noc design point,network traffic,suitable interconnection network design,complicated noc,network design,actual design process,system-level roadmapping toolchain,detailed noc synthesis result,on-chip interconnection network,topology,cost effectiveness,computer architecture,network on chip,simulation software,chip,design process,simulation,system design,system on a chip | System on a chip,Network planning and design,Computer science,Network architecture,Network on a chip,Real-time computing,Electronic engineering,Design process,Interconnection,Toolchain,Scalability,Embedded system | Journal |
Volume | Issue | ISSN |
15 | 8 | 1063-8210 |
Citations | PageRank | References |
8 | 0.70 | 23 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vassos Soteriou | 1 | 421 | 27.62 |
| Noel Eisley | 2 | 270 | 18.35 |
| Hangsheng Wang | 3 | 861 | 59.21 |
| Bin Li | 4 | 40 | 3.29 |
| Li-Shiuan Peh | 5 | 5077 | 398.57 |