Title
Optimizing high speed arithmetic circuits using three-term extraction
Abstract
Carry Save Adder (CSA) trees are commonly used for high speed implementation of multi-operand additions. We present a method to reduce the number of the adders in CSA trees by extracting common three-term subexpressions. Our method can optimize multiple CSA trees involving any number of variables. This optimization has a significant impact on the total area of the synthesized circuits, as we show in our experiments. To the best of our knowledge, this is the only known method for eliminating common subexpressions in CSA structures. Since extracting common subexpressions can potentially increase delay, we also present a delay aware extraction algorithm that takes into account the different arrival times of the signals.
Year
DOI
Venue
2006
10.1109/DATE.2006.244103
DATE
Keywords
Field
DocType
high speed arithmetic circuit,common subexpressions,delay aware extraction algorithm,common three-term subexpressions,multi-operand addition,csa structure,high speed implementation,carry save adder,multiple csa tree,different arrival time,three-term extraction,csa tree,semiconductor devices,design automation,computer applications,arithmetic,adders
Arithmetic circuits,Adder,Computer science,Extraction algorithm,Real-time computing,Electronic design automation,Carry-save adder,Computer Applications,Electronic circuit
Conference
ISSN
ISBN
Citations 
1530-1591
3-9810801-0-6
5
PageRank 
References 
Authors
0.55
11
3
Name
Order
Citations
PageRank
Anup Hosangadi11129.01
Farzan Fallah255743.73
Ryan Kastner31779147.73