Paper Info
Title
Checking Sequence Generation Using State Distinguishing Subsequences
Abstract
A checking sequence generated from a Finite State Machine (FSM) is used in testing to demonstrate correctness of an implementation under test. It can be obtained by concatenating inputs triggering state transitions followed by final state verification sequences. Usually, the latter are derived from a distinguishing set or sequence, assuming that a given FSM possesses it. It has been suggested that, under certain conditions, Unique Input/Output (UIO) sequences can also be used. In this paper, we propose using sequences with less state distinguishability power than distinguishing and UIO sequences. Such sequences are shorter and thus can reduce the length of checking sequences. We formulate conditions under which such sequences can replace distinguishing and UIO sequences and elaborate a checking sequence generation method based on these conditions. An example is provided to demonstrate that the proposed method yields a checking sequence shorter than existing methods.
Year
DOI
Venue
2009
10.1109/ICSTW.2009.25
ICST Workshops
Keywords
Field
DocType
distinguishing set,uio sequence,checking sequence generation,proposed method yield,state distinguishing subsequences,certain condition,checking sequence generation method,unique input,checking sequence,finite state machine,state distinguishability power,final state verification sequence,testing,delta modulation,automata,input output,finite state machines,state transition,data mining,probability density function,software testing,logic design
Logic synthesis,Computer science,Delta modulation,Automaton,Implementation under test,Correctness,Algorithm,Finite-state machine,Concatenation,Probability density function
Conference
ISSN
Citations 
PageRank 
2159-4848
8
0.49
References 
Authors
17
2
Name
Order
Citations
PageRank
Adenilso Simão1261.87
Alexandre Petrenko217615.90