Name
Abstract | ||
|---|---|---|
The concept of local design rules is introduced. These are integrated circuit (IC) layout rules that define the optimum feature size and spacing in relation to the surrounding geometry and are used to increase the yield of ICs. The impact of these rules on the performance and reliability of ICs is discussed. Algorithms that enable the automatic application of track displacement, track width, and contact size local design rules to IC layout are presented. Simulation results are provided for some layout examples |
Year | DOI | Venue |
|---|---|---|
1992 | 10.1109/43.177399 | Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions |
Keywords | DocType | Volume |
contact size local design,optimum feature size,track displacement,layout example,automatic application,local design rule,IC layout,yield improvement technique,integrated circuit,track width,layout rule | Journal | 11 |
Issue | ISSN | Citations |
11 | 0278-0070 | 11 |
PageRank | References | Authors |
0.98 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| G. A. Allan | 1 | 30 | 3.77 |
| Anthony J. Walton | 2 | 35 | 6.28 |
| R. J. Holwill | 3 | 11 | 0.98 |