Name
Abstract | ||
|---|---|---|
This paper presents a hardware architecture for face detection based on the Viola and Jones object detection method. To achieve high speed detection, two major features are introduced in this paper, including rapid integral image generation and hybrid stage classifier. A register array structure is utilized for storing and generating integral image, facilitating the simultaneous access and parallel classifier evaluation. Moreover, a hybrid stage classifier is proposed which combines both serial processing and parallel processing, making the best trade-off between detection speed and resource consumption. In addition, the detection system can detect human faces in a 384×288 image at a speed of 22 fps when the specialized processor in a Stratix II FPGA works at 100 MHz. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ICECS.2012.6463524 | ICECS |
Keywords | DocType | Volume |
face detection,hardware architecture,parallel processing,register array structure,face recognition,high speed detection,microprocessor chips,stratix ii fpga,detection speed,haar-like features,resource consumption,highly parallelized processor,image classification,parallel classifier evaluation,detection system,object detection,rapid integral image generation,haar transforms,field programmable gate arrays,object detection method,frequency 100 mhz,serial processing,hybrid stage classifier | Conference | null |
Issue | ISBN | Citations |
null | 978-1-4673-1259-2 | 1 |
PageRank | References | Authors |
0.38 | 5 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Huabiao Qin | 1 | 9 | 3.92 |
| Lianbing Tian | 2 | 1 | 0.38 |
| Zongwei Hu | 3 | 1 | 0.38 |