Paper Info
Title
Automatic post-layout flow validation tool for Deep Sub-micron process design kits
Abstract
This paper presents a novel automated post-layout flow validation tool to intensively test the MOSFETs and passive components in 32nm, 28nm and 22nm Process Design Kits (PDK). Benchmark circuits, such as, ring oscillator, logic circuits and passive delay circuits, are automatically generated, LVS (layout versus schematic) checked, extracted and simulated in multiple Model/LVS/Parasitic extraction(PEX) test flows. By using the proposed tool, the delay differences (deltas) between the different test flows are cross verified to assure the functionality and accuracy of Model, LVS and PEX before PDK release. Combined with field solver validation, the automated post-layout flow validation significantly improves the quality and reduces the development time of Deep Submicron (DSM) PDKs.
Year
DOI
Venue
2011
10.1109/ISQED.2011.5770769
ISQED
Keywords
Field
DocType
logic circuits,automatic post-layout flow validation tool,deep submicron process design kit,tool validation,size 22 nm,pex,layout versus schematic,size 28 nm,process design,parasitic extraction (pex),process design kits (pdk),semiconductor device testing,deep submicron (dsm),ring oscillator,size 32 nm,benchmark circuit,circuit cad,integrated circuit design,pdk,lvs,mosfet,model-lvs-parasitic extraction,dsm,delay differences (deltas),passive delay circuit,circuit simulation,capacitance,benchmark testing,accuracy,layout,resistance,integrated circuit
Logic gate,Ring oscillator,Layout Versus Schematic,Computer science,Electronic engineering,Integrated circuit design,Process design,Electronic component,Parasitic extraction,Benchmark (computing)
Conference
ISSN
ISBN
Citations 
1948-3287
978-1-61284-913-3
0
PageRank 
References 
Authors
0.34
2
7
Name
Order
Citations
PageRank
Pinping Sun131.22
Cole Zemke200.34
Wayne H. Woods310.74
Nick Perez400.34
Hailing Wang595.07
Essam Mina600.34
Barbara Dewitt700.34