Paper Info
Title
An 8MHz 75µA/MHz zero-leakage non-volatile logic-based Cortex-M0 MCU SoC exhibiting 100% digital state retention at VDD=0V with <400ns wakeup and sleep transitions
Abstract
We demonstrate a non-volatile logic (NVL)-based SoC that backs up its working state (all flip-flops) upon receiving a power interrupt, has zero leakage in sleep mode, and needs less than 400ns to restore the system state upon power-up. Without NVL, a chip would either have to keep all flip-flops powered resulting in high standby power, or waste energy and time rebooting after power-up. For energy harvesting applications, NVL is a “must have” because there is no constant power source available to keep flip-flops (FFs) alive, and even when the intermittent power source is available, boot-up code alone may consume all of the harvested energy. For handheld devices with limited cooling and battery capacity, zero-leakage IC's with “instant-on” capability are ideal.
Year
DOI
Venue
2013
10.1109/ISSCC.2013.6487802
Solid-State Circuits Conference Digest of Technical Papers
Keywords
Field
DocType
flip-flops,logic circuits,microcontrollers,system-on-chip,battery capacity,digital state retention,flip-flops,frequency 8 MHz,instant-on capability,intermittent power source,sleep mode,time rebooting,voltage 0 V,waste energy,zero-leakage IC,zero-leakage nonvolatile logic-based Cortex-M0 MCU SoC
Interrupt,Reboot,Logic gate,System on a chip,Standby power,Leakage (electronics),Computer science,Energy harvesting,Electronic engineering,Sleep mode,Electrical engineering,Embedded system
Conference
ISSN
ISBN
Citations 
0193-6530
978-1-4673-4515-6
3
PageRank 
References 
Authors
0.41
0
6
Name
Order
Citations
PageRank
steven craig bartling130.41
Sudhanshu Khanna2558.45
Michael Clinton3449.26
Scott R. Summerfelt461.93
John Rodriguez59153.59
Hugh P. McAdams651.52