Name
Abstract | ||
|---|---|---|
With the advent of multicore architectures, especially with the heterogeneous ones, both computational and memory top performance are difficult to obtain using traditional programming models. Usually, programmers have to fully reorganize the code and data of their applications in order to maximize resource usage, and work with the low-level interfaces offered by the vendor-provided SDKs, to obtain high computational and memory performances. In this paper, we present the evaluation of the SARC programming model on the Cell BE architecture, with respect to memory performance. We show how we have annotated the HPL STREAM and RandomAccess applications, and the memory bandwidth obtained. Results indicate that the programming model provides good productivity and competitive performance on this kind of architectures. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1509084.1509095 | Proceedings of the 9th workshop on MEmory performance: DEaling with Applications, systems and architecture |
Keywords | DocType | Citations |
traditional programming model,memory bandwidth,high computational,randomaccess application,memory top performance,competitive performance,hpl stream,memory performance,programming model,sarc programming model,programming models,hardware transactional memory | Conference | 6 |
PageRank | References | Authors |
0.59 | 12 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Roger Ferrer | 1 | 39 | 4.04 |
| Marc González | 2 | 187 | 17.61 |
| Federico Silla | 3 | 576 | 56.77 |
| Xavier Martorell | 4 | 1470 | 125.40 |
| Eduard Ayguadé | 5 | 2406 | 216.00 |