Name
Abstract | ||
|---|---|---|
A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy post-fabrication tuning scheme has been developed. Based on the proposed techniques, 61% improvement of the sensing accuracy is realized. Even with the smallest 5 fF/cell capacitance, a 322 MHz random-cycle access while 32 ms data retention time which contributes to sav... |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/JSSC.2005.857358 | IEEE Journal of Solid-State Circuits |
Keywords | DocType | Volume |
Random access memory,CMOS process,Capacitance,Logic,Costs,Large scale integration,Noise generators,Noise level,Semiconductor device noise,Delay | Journal | 40 |
Issue | ISSN | Citations |
11 | 0018-9200 | 6 |
PageRank | References | Authors |
3.12 | 1 | 17 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| M. Iida | 1 | 6 | 3.12 |
| N. Kuroda | 2 | 6 | 3.46 |
| H. Otsuka | 3 | 6 | 3.12 |
| M. Hirose | 4 | 6 | 3.12 |
| Y. Yamasaki | 5 | 6 | 3.12 |
| K. Ohta | 6 | 6 | 3.12 |
| K. Shimakawa | 7 | 6 | 3.12 |
| T. Nakabayashi | 8 | 6 | 3.12 |
| H. Yamauchi | 9 | 6 | 3.12 |
| TOSHIAKI SANO | 10 | 17 | 5.52 |
| T. Gyohten | 11 | 15 | 4.30 |
| M. Maruta | 12 | 7 | 3.61 |
| A. Yamazaki | 13 | 6 | 3.46 |
| F. Morishita | 14 | 6 | 3.12 |
| K. Dosaka | 15 | 24 | 5.27 |
| M. Takeuchi | 16 | 7 | 3.48 |
| K. Arimoto | 17 | 15 | 4.64 |