Name
Abstract | ||
|---|---|---|
We describe a class-specific linear pseudosystolic array, withK processing elements, suitable for partitioned execution of matrix algorithms. This array achieves high efficiency, exploits pipelining within cells in a simple manner, has off-cells communication rate lower than computation rate, a small storage inside each cell (whose size is independent of the size of problems), and external storage. This array has been derived from the application of the multimesh graph (MMG) method to a large class of matrix algorithms. |
Year | DOI | Venue |
|---|---|---|
1991 | 10.1007/BF00925831 | VLSI Signal Processing |
Keywords | Field | DocType |
Systolic Array,Memory Module,Pipeline Stage,Matrix Algorithm,FIFO Queue | Pipeline (computing),Sparse array,Computer science,Instruction set,Parallel computing,Systolic array,Algorithm,Real-time computing,Model of computation,External storage,Block matrix,Memory module | Journal |
Volume | Issue | Citations |
3 | 3 | 0 |
PageRank | References | Authors |
0.34 | 9 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jamie H. Moreno | 1 | 0 | 0.34 |
| Miguel E. Figueroa | 2 | 23 | 2.45 |
| Tomas Lang | 3 | 0 | 0.34 |