Name
Abstract | ||
|---|---|---|
Next generation Internet requires processing rich and flexible flow information in the network infrastructure. Rapid growth in network traffic results in major challenge to support flexible flow matching at line rate. Most of the existing work focuses on functionality rather than performance, and simply adopts either power-hungry TCAM or performance-in deterministic hashing. This paper exploits the abundant parallelism and other desirable features provided by state-of-the-art FPGAs, and proposes a parallel architecture, named decision forest, for high-performance flexible flow matching. We develop a framework to partition a given table of flexible flow rules into multiple subsets each of which is built into a depth-bounded decision tree. The partitioning scheme is carefully designed to reduce rule duplication during the construction of the decision trees. Thus the overall memory requirement is significantly reduced. After such partitioning, the number of header fields used to build the decision tree for each rule subset is small. This leads to reduction in logic resource requirement. Exploiting the dual-port RAMs available in current FPGAs, we map each decision tree onto a linear pipeline to achieve high throughput. Our extensive experiments and FPGA implementation demonstrate the effectiveness of our scheme. Our design supports 1K flexible flow rules while sustaining 40 Gbps throughput for matching minimum size (40 bytes) packets. To the best of our knowledge, this is the first FPGA design for flexible flow matching to achieve over 10 Gbps. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/FPL.2010.83 | FPL |
Keywords | Field | DocType |
scalable architecture,flexible flow rule,decision forest,flexible flow information,flexible flow matching,fpga design,depth-bounded decision tree,decision tree,high-performance flexible flow matching,gbps throughput,flexible flow,fpga implementation,high throughput,switches,decision trees,internet,field programmable gate arrays,openflow,pipelines,memory management,throughput,fpga | Decision tree,Computer science,Network packet,Parallel computing,Field-programmable gate array,Real-time computing,Memory management,Hash function,Throughput,Header,Random forest | Conference |
Citations | PageRank | References |
6 | 0.63 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Weirong Jiang | 1 | 521 | 32.11 |
| Viktor K. Prasanna | 2 | 7211 | 762.74 |
| Norio Yamagaki | 3 | 54 | 4.84 |