Name
Abstract | ||
|---|---|---|
To bridge the widening gap between computation requirements of terascale application and communication efficiency faced by many-core processor chips, wireless Network-on-Chip (WiNoC) has been proposed by using the recently developed CMOS ultra wideband interconnection. In this research, we propose an unequal RF nodes overlaid mesh topology design to improve the on-chip communication performance. A network capacity model is developed for fast searching of optimal topology configuration. A high-efficient, low-cost zone-aided routing scheme is designed to facilitate deadlock freedom. The simulation study demonstrates topology modeling effectiveness, routing efficiency, and promising network performance of the overlaid mesh WiNoC over a regular 2D mesh baseline. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/NOCS.2012.11 | NOCS |
Keywords | Field | DocType |
deadlock freedom,cmos integrated circuits,zone aided routing,integrated circuit interconnections,network routing,deadlock free routing,routing efficiency,many-core processor chips,overlaid mesh topology design,topology design,overlaid mesh topology,topology modeling effectiveness,zone aided routing scheme,network topology,wireless network-on-chip,communication efficiency,mesh baseline,cmos ultra wideband interconnection,low-cost zone-aided routing scheme,overlaid mesh winoc,octagon turn model,promising network performance,deadlock avoidance,optimal topology configuration,network capacity model,2d mesh baseline,network-on-chip,on-chip communication performance,radio frequency,network on chip,wireless communication,topology,bandwidth,routing | Switched mesh,Mesh networking,Computer science,Deadlock,Computer network,Network on a chip,Network topology,Wireless mesh network,Shared mesh,Network performance | Conference |
ISBN | Citations | PageRank |
978-1-4673-0973-8 | 6 | 0.71 |
References | Authors | |
5 | 2 | |