Name
Title | ||
|---|---|---|
Energy consumption reduction mechanism by tuning cache configuration usign NIOS II processor |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/SOCC.2008.4641530 | SoCC |
Keywords | Field | DocType |
embedded system,field programmable gate arrays,system on chip,fpga,embedded systems,design flow | Memory hierarchy,System on a chip,Suite,Cache,Computer science,Field-programmable gate array,Design flow,Computer hardware,Nios II,Energy consumption,Embedded system | Conference |
Citations | PageRank | References |
1 | 0.37 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Abel Guilhermino Silva-Filho | 1 | 62 | 12.94 |
| Sidney M. L. Lima | 2 | 15 | 2.25 |