Name
Abstract | ||
|---|---|---|
Early-life failures (ELF) result from weak chips that may pass manufacturing tests but fail early in the field, much earlier than expected product lifetime. Recent experimental studies over a range of technologies have demonstrated that ELF defects result in changes in delays over time inside internal nodes of a logic circuit before functional failure occurs. Such changes in delays are distinct from delay degradation caused by circuit aging mechanisms such as Bias Temperature Instability. Traditional transition fault or robust path delay fault test patterns are inadequate for detecting such ELF-induced changes in delays because they do not model the demanding detection conditions precisely. In this paper, we present an automatic test pattern generation (ATPG) technique based on Boolean Satisfiability (SAT) for detecting ELF-induced delay changes at all gates in a given circuit. Our simulation results, using various circuit blocks from the industrial OpenSPARC T2 design as well as standard benchmarks, demonstrate the effectiveness and practicality of our approach in achieving high coverage of ELF-induced delay change detection. We also demonstrate the robustness of our approach to manufacturing process variations. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TEST.2013.6651925 | Test Conference |
Keywords | Field | DocType |
automatic test pattern generation,computability,failure analysis,integrated circuit design,manufacturing processes,Boolean satisfiability,ELF-induced delay change detection,SAT-based ATPG,automatic test pattern generation technique,bias temperature instability,circuit aging mechanisms,circuit blocks,delay degradation,early-life-failure detection,functional failure,industrial OpenSPARC T2 design,internal nodes,logic circuit,manufacturing process variations,robust path delay fault test patterns,standard benchmarks,transition fault | Stuck-at fault,Automatic test pattern generation,Change detection,Fault coverage,Computer science,Circuit extraction,Boolean satisfiability problem,Electronic engineering,Real-time computing,Robustness (computer science),Integrated circuit design | Conference |
ISSN | Citations | PageRank |
1089-3539 | 4 | 0.42 |
References | Authors | |
0 | 9 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Matthias Sauer | 1 | 195 | 20.02 |
| Young Moon Kim | 2 | 216 | 11.24 |
| Jun Seomun | 3 | 64 | 5.87 |
| Hyung-Ock Kim | 4 | 67 | 6.73 |
| Kyung Tae Do | 5 | 22 | 3.46 |
| Jung Yun Choi | 6 | 32 | 5.26 |
| Kee Sup Kim | 7 | 648 | 39.43 |
| Subhasish Mitra | 8 | 3657 | 228.90 |
| B. Becker | 9 | 191 | 21.44 |