Title
Accelerated concurrent fault simulation by analyzing detected faults
Year
DOI
Venue
1997
10.1002/(SICI)1520-684X(199704)28:4<68::AID-SCJ7>3.0.CO;2-N
Systems and Computers in Japan
Keywords
Field
DocType
logic circuit
Logic gate,Fault coverage,Computer science,Algorithm,Acceleration,Network analysis,Electronic circuit,Time complexity,Integrated circuit,Computation
Journal
Volume
Issue
Citations 
28
4
0
PageRank 
References 
Authors
0.34
9
2
Name
Order
Citations
PageRank
Yukio Ishibashi141.62
Masahiro Nagamatsu201.69