Name
Abstract | ||
|---|---|---|
In a superscalar processor, select logic within the critical path of the instruction queue has become a performance bottleneck. This paper presents a high speed, two-level, hybrid select logic for wide-issue processors. The first level reduces delay by performing parallel age-based selection, and final arbitration is achieved in the second level with simple position-based select logic. The hybrid select logic circuits were implemented in dynamic logic on IBM 0.13mum technology. Simulation shows 36% reduction in delay with less than 1% IPC degradation compared to the conventional design |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/ISCAS.2006.1692517 | ISCAS |
Keywords | Field | DocType |
logic circuits,ibm technology,microprocessor chips,parallel age-based selection,wide-issue processors,superscalar processors,hybrid select logic circuits,position-based select logic,logic design,critical path,instruction queue,0.13 micron,degradation,tail,computer aided manufacturing | Logic synthesis,Logic gate,Computer architecture,Sequential logic,Logic optimization,Computer science,Parallel computing,Logic level,Logic family,Critical path method,Dynamic logic (digital electronics) | Conference |
ISSN | ISBN | Citations |
0271-4302 | 0-7803-9389-9 | 1 |
PageRank | References | Authors |
0.38 | 1 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Junwei Zhou | 1 | 118 | 16.64 |
| Andrew Mason | 2 | 24 | 4.66 |